//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef __ELASTOS_INSTRUCTION_H__
#define __ELASTOS_INSTRUCTION_H__

typedef void    *vaddr_t_l;
#define         EFAULT  1

//
// Major opcodes; before MIPS IV cop1x was called cop3.
//
enum major_op
{
    // 0x00 ~ 0x03
    spec_op, bcond_op, j_op, jal_op,
    // 0x04 ~ 0x07
    beq_op, bne_op, blez_op, bgtz_op,
    // 0x08 ~ 0x0b
    addi_op, addiu_op, slti_op, sltiu_op,
    // 0x0c ~ 0x0f
    andi_op, ori_op, xori_op, lui_op,
    // 0x10 ~ 0x13
    cop0_op, cop1_op, cop2_op, cop1x_op,
    // 0x14 ~ 0x17
    beql_op, bnel_op, blezl_op, bgtzl_op,
    // 0x18 ~ 0x1b
    daddi_op, daddiu_op, ldl_op, ldr_op,
    // 0x1c ~ 0x1f
    major_1c_op, jalx_op, major_1e_op, major_1f_op,
    // 0x20 ~ 0x23
    lb_op, lh_op, lwl_op, lw_op,
    // 0x24 ~ 0x27
    lbu_op, lhu_op, lwr_op, lwu_op,
    // 0x28 ~ 0x2b
    sb_op, sh_op, swl_op, sw_op,
    // 0x2c ~ 0x2f
    sdl_op, sdr_op, swr_op, cache_op,
    // 0x30 ~ 0x33
    ll_op, lwc1_op, lwc2_op, pref_op,
    // 0x34 ~ 0x37
    lld_op, ldc1_op, ldc2_op, ld_op,
    // 0x38 ~ 0x3b
    sc_op, swc1_op, swc2_op, major_3b_op,   // Opcode 0x3b is unused
    // 0x3c ~ 0x3f
    scd_op, sdc1_op, sdc2_op, sd_op
};

/*
 * func field of spec opcode.
 */
enum spec_op
{
    sll_op, movc_op, srl_op, sra_op,
    sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */
    jr_op, jalr_op, movz_op, movn_op,
    syscall_op, break_op, spim_op, sync_op,
    mfhi_op, mthi_op, mflo_op, mtlo_op,
    dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
    mult_op, multu_op, div_op, divu_op,
    dmult_op, dmultu_op, ddiv_op, ddivu_op,
    add_op, addu_op, sub_op, subu_op,
    and_op, or_op, xor_op, nor_op,
    spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
    dadd_op, daddu_op, dsub_op, dsubu_op,
    tge_op, tgeu_op, tlt_op, tltu_op,
    teq_op, spec5_unused_op, tne_op, spec6_unused_op,
    dsll_op, spec7_unused_op, dsrl_op, dsra_op,
    dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
};

/*
 * rt field of bcond opcodes.
 */
enum rt_op
{
    bltz_op, bgez_op, bltzl_op, bgezl_op,
    spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
    tgei_op, tgeiu_op, tlti_op, tltiu_op,
    teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
    bltzal_op, bgezal_op, bltzall_op, bgezall_op
    /*
     * The others (0x14 - 0x1f) are unused.
     */
};

/*
 * rs field of cop opcodes.
 */
enum cop_op
{
    mfc_op        = 0x00, dmfc_op       = 0x01,
    cfc_op        = 0x02, mtc_op        = 0x04,
    dmtc_op       = 0x05, ctc_op        = 0x06,
    bc_op         = 0x08, cop_op        = 0x10,
    copm_op       = 0x18
};

/*
 * rt field of cop.bc_op opcodes
 */

enum bcop_op
{
    bcf_op, bct_op, bcfl_op, bctl_op
};

/*
 * func field of cop0 coi opcodes.
 */
enum cop0_coi_func
{
    tlbr_op       = 0x01, tlbwi_op      = 0x02,
    tlbwr_op      = 0x06, tlbp_op       = 0x08,
    rfe_op        = 0x10, eret_op       = 0x18
};

/*
 * func field of cop0 com opcodes.
 */
enum cop0_com_func
{
    tlbr1_op      = 0x01, tlbw_op       = 0x02,
    tlbp1_op      = 0x08, dctr_op       = 0x09,
    dctw_op       = 0x0a
};

/*
 * fmt field of cop1 opcodes.
 */
enum cop1_fmt
{
    s_fmt, d_fmt, e_fmt, q_fmt,
    w_fmt, l_fmt
};

/*
 * func field of cop1 instructions using d, s or w format.
 */
enum cop1_sdw_func
{
    fadd_op      =  0x00, fsub_op      =  0x01,
    fmul_op      =  0x02, fdiv_op      =  0x03,
    fsqrt_op     =  0x04, fabs_op      =  0x05,
    fmov_op      =  0x06, fneg_op      =  0x07,
    froundl_op   =  0x08, ftruncl_op   =  0x09,
    fceill_op    =  0x0a, ffloorl_op   =  0x0b,
    fround_op    =  0x0c, ftrunc_op    =  0x0d,
    fceil_op     =  0x0e, ffloor_op    =  0x0f,
    fmovc_op     =  0x11, fmovz_op     =  0x12,
    fmovn_op     =  0x13, frecip_op    =  0x15,
    frsqrt_op    =  0x16, fcvts_op     =  0x20,
    fcvtd_op     =  0x21, fcvte_op     =  0x22,
    fcvtw_op     =  0x24, fcvtl_op     =  0x25,
    fcmp_op      =  0x30
};

/*
 * func field of cop1x opcodes (MIPS IV).
 */
enum cop1x_func
{
    lwxc1_op     =  0x00, ldxc1_op     =  0x01,
    pfetch_op    =  0x07, swxc1_op     =  0x08,
    sdxc1_op     =  0x09, madd_s_op    =  0x20,
    madd_d_op    =  0x21, madd_e_op    =  0x22,
    msub_s_op    =  0x28, msub_d_op    =  0x29,
    msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
    nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
    nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
    nmsub_e_op   =  0x3a
};

/*
 * func field for mad opcodes (MIPS IV).
 */
enum mad_func
{
    madd_op      = 0x08, msub_op      = 0x0a,
    nmadd_op     = 0x0c, nmsub_op     = 0x0e
};

// It's mipsel
struct j_format
{   /* Jump format */
    unsigned int target : 26;
    unsigned int opcode : 6;
};

struct i_format
{   /* Immediate format */
    signed int simmediate : 16;
    unsigned int rt : 5;
    unsigned int rs : 5;
    unsigned int opcode : 6;
};

struct u_format
{   /* Unsigned immediate format */
    unsigned int uimmediate : 16;
    unsigned int rt : 5;
    unsigned int rs : 5;
    unsigned int opcode : 6;
};

struct c_format
{   /* Cache (>= R6000) format */
    unsigned int simmediate : 16;
    unsigned int cache : 2;
    unsigned int c_op : 3;
    unsigned int rs : 5;
    unsigned int opcode : 6;
};

struct r_format
{   /* Register format */
    unsigned int func : 6;
    unsigned int re : 5;
    unsigned int rd : 5;
    unsigned int rt : 5;
    unsigned int rs : 5;
    unsigned int opcode : 6;
};

struct p_format
{   /* Performance counter format (R10000) */
    unsigned int func : 6;
    unsigned int re : 5;
    unsigned int rd : 5;
    unsigned int rt : 5;
    unsigned int rs : 5;
    unsigned int opcode : 6;
};

struct f_format
{   /* FPU register format */
    unsigned int func : 6;
    unsigned int re : 5;
    unsigned int rd : 5;
    unsigned int rt : 5;
    unsigned int fmt : 4;
    unsigned int : 1;
    unsigned int opcode : 6;
};

struct ma_format
{  /* FPU multipy and add format (MIPS IV) */
    unsigned int fmt : 2;
    unsigned int func : 4;
    unsigned int fd : 5;
    unsigned int fs : 5;
    unsigned int ft : 5;
    unsigned int fr : 5;
    unsigned int opcode : 6;
};

union unionMipsInstruction
{
    unsigned int word;
    unsigned short halfword[2];
    unsigned char byte[4];
    struct j_format j_format;
    struct i_format i_format;
    struct u_format u_format;
    struct c_format c_format;
    struct r_format r_format;
    struct f_format f_format;
    struct ma_format ma_format;
};

#ifdef _DEBUG
#define CHECK_DATA_NOT_ALIGN(data, align)       \
    if (!(data & align)) {                      \
        DebugBreak();                           \
    }
#else
#define CHECK_DATA_NOT_ALIGN(data, align)
#endif

#endif // __ELASTOS_INSTRUCTION_H__
